1. Field of the Invention
The present invention relates to a method of manufacturing a trench structure for a device for forming a trench interconnection element such as a damascene structure.
2. Description of the Related Art
In the manufacturing process of a semiconductor device, a single damascene process or a dual damascene process is widely employed for forming a multilevel interconnection. FIGS. 8A to 8E collectively exemplify a process of forming a multilevel interconnection by the single damascene process. In the first step, a lower interconnection 93 made of, for example, copper is formed in a surface portion of a dielectric film 91 formed on a semiconductor wafer W (not shown) with a barrier metal layer 92 interposed between the dielectric film 91 and the lower interconnection 93, followed by forming a dielectric film 94 on the surfaces of the dielectric film 91 including the lower interconnection 93 and subsequently forming a bottom anti-reflective coating (BARC) film 95, as shown in FIG. 8A. Further, a resist film 96 is formed on the BARC film 95.
In the next step, the resist film 96 is exposed in a prescribed circuit pattern, followed by developing the resist film so as to form a prescribed circuit pattern in the resist film 96, as shown in FIG. 8B. The wafer W thus obtained is etched so as to form a via hole 94a in the dielectric film 94. The etching treatment is continued until the via hole 94a extends to permit the lower interconnection 93 to be exposed to the outside, as shown in FIG. 8C. Then, the resist film 96 is dissolved in a solvent so as to be removed, as shown in FIG. 8D.
Further, an electrically conductive thin film is formed until the via hole 94a is filled with an electrically conductive material 94b, as shown in FIG. 8E. Then, a planarizing treatment such as a CMP (Chemical Mechanical Polishing) treatment is applied so as to remove the BARC film 95 from the wafer W and to form a trench interconnection that permits the lower interconnection 93 to be electrically connected to the electrically conductive material 94b within the via hole 94a. The particular method of forming a trench interconnection element is disclosed in, for example, JP 2000-232106.
In the development of a semiconductor device using such a damascene process, a dielectric film having a low dielectric constant such as a low-k film or a low-ε film has come to be used for forming the dielectric film 94 in an attempt to improve the speed of the arithmetic processing or to lower the power consumption. Further, in the development in recent years of a semiconductor device such as an LSI, it is attempted to use a porous low-k film having a relative dielectric constant much lower than that of the conventional low-k film for forming the dielectric film 94 in order to improve the speed of the arithmetic processing.
However, where a porous low-k film is formed and a via hole is formed in the porous low-k film by the damascene process described above, the porous low-k film is corroded in the subsequent step of removing the resist film by the treatment with a chemical liquid, giving rise to the problem that the shape of the via hole cannot be retained.
Also, as another method of removing the resist film, known is a method of removing the resist film 96 by an ashing treatment. However, the porous low-k film tends to incur damages by the ashing treatment so as to give rise to the problems that the dielectric constant is increased and that it is difficult to maintain the dimensional accuracy in the shape of the trench. In addition, the ashing treatment is defective in that the through-put is low.